A Single-Multiplier Quadratic Interpolator for LNS Arithmetic

نویسندگان

  • Mark G. Arnold
  • Mark D. Winkel
چکیده

Linear interpolation requires a single multiplication but is signiicantly less accurate than quadratic interpolation. The latter requires two multiplications. Two novel quadratic interpolation schemes are shown here that approximate the functions required by the Logarithmic Number System (LNS) with more accuracy than linear interpolation using only a single multiplication. One method uses two ROMs to give the accuracy of quadratic interpolation, whilst the other uses one ROM to give four-to six-bits better accuracy than linear interpolation. These techniques save four-to eight-fold on memory compared to linear interpolation for the same accuracy. We illustrate the usefulness of these techniques for serial implementation with a clone of the ARM TM microprocessor (known as AWE) that we developed to have LNS instructions. We also show a novel technique for decreasing the propagation delay in both linear and quadratic interpolation that stores the logarithm of the derivative of the function in a ROM, rather than the function itself.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design of a Faithful LNS Interpolator

A design is given for a quadratic interpolator needed by the Logarithmic Number System (LNS). Unlike previous LNS designs that have attempted to produce results consistently better than a oating-point representation of the same word size (32 bits), the design goal here is to minimize memory requirements and system complexity, at the expense of a slight increase in approximation error. Simulatio...

متن کامل

FPGA based Efficient Interpolator design using DALUT Algorithm

Abstract: Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient i...

متن کامل

Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...

متن کامل

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimiz...

متن کامل

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers

This paper presents a technique for designing linear and quadratic interpolators for function approximation using truncated multipliers and squarers. Initial coefficient values are found using a Chebyshev-series approximation and then adjusted through exhaustive simulation to minimize the maximum absolute error of the interpolator output. This technique is suitable for any function and any prec...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2001